A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power estimation techniques for integrated circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Power optimization of variable voltage core-based systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
On-line scheduling of hard real-time tasks on variable voltage processor
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Optimal voltage allocation techniques for dynamically variable voltage processors
Proceedings of the 40th annual Design Automation Conference
Minimizing Energy Consumption for High-Performance Processing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Application-directed voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Reduced energy decoding of MPEG streams
Multimedia Systems
Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems
IEEE Transactions on Computers
Low power operating system for heterogeneous wireless communication system
Compilers and operating systems for low power
A methodology for low power scheduling with resources operating at multiple voltages
Integration, the VLSI Journal
A framework for energy and transient power reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal voltage allocation techniques for dynamically variable voltage processors
ACM Transactions on Embedded Computing Systems (TECS)
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages
IEEE Transactions on Computers
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages
The Journal of Supercomputing
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On multiple-voltage high-level synthesis using algorithmic transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints
Integration, the VLSI Journal
Multiple voltage synthesis scheme for low power design under timing and resource constraints
Integrated Computer-Aided Engineering
Power optimization for simultaneous scheduling and partitioning with multiple voltages
MMACTE'05 Proceedings of the 7th WSEAS International Conference on Mathematical Methods and Computational Techniques In Electrical Engineering
WSEAS Transactions on Signal Processing
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
An energy and power-aware approach to high-level synthesis of asynchronous systems
Proceedings of the International Conference on Computer-Aided Design
Temperature aware datapath scheduling
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. Experimental results show that our heuristic produces results competitive with those of the ILP method in a fraction of the run-time. The results also show that a wide range of design alternatives can be generated using our design space exploration method. Using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3V and 5V supply voltages.