DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
IEEE Transactions on Computers
FPGA clock management for low power applications (poster abstract)
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Voltage scheduling in the IpARM microprocessor system
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A low-redundancy approach to semi-concurrent error detection in data paths
Proceedings of the conference on Design, automation and test in Europe
Nonideal battery and main memory effects on CPU speed-setting for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Dynamic voltage scaling on a low-power microprocessor
Proceedings of the 7th annual international conference on Mobile computing and networking
Energy priority scheduling for variable voltage processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Energy efficient CMOS microprocessor design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Energy Efficient Scheduling for Datapath Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Datapath Scheduling using Dynamic Frequency Clocking
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Policies for dynamic clock scheduling
OSDI'00 Proceedings of the 4th conference on Symposium on Operating System Design & Implementation - Volume 4
Telescopic units: a new paradigm for performance optimization of VLSI designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear array processor with dynamic frequency clocking for image processing applications
IEEE Transactions on Circuits and Systems for Video Technology
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Recently, dynamic frequency scaling has been explored at the CPU and system levels for power optimization. Low-power datapath scheduling using multiple supply voltages has been well researched. In this work, we develop new datapath scheduling algorithms that use multiple supply voltages and dynamic frequency clocking in a coordinated manner in order to reduce the energy consumption of datapath circuits. In dynamic frequency clocking, the functional units can be operated at different frequencies depending on the computations occurring within the datapath during a given clock cycle. The strategy is to schedule high-energy units, such as multipliers at lower frequencies, so that they can be operated at lower voltages to reduce energy consumption and the low-energy units, such as adders at higher frequencies, to compensate for speed. The proposed time- and resource-constrained algorithms have been applied to various high-level synthesis benchmark circuits under different time and resource constraints. The experimental results show significant reduction in energy for both the algorithms.