High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A high-level synthesis approach to optimum design of self-checking circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
Self-checking FSMs based on a constant distance state encoding
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Optimizing High-Level Synthesis for Self-Checking Arithmetic Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
A high-level synthesis approach to design of fault-tolerant systems
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A high-level synthesis approach is proposed for design of semi-concurrently self-checking devices; attention is focussed on data path design. After identifying the reference architecture against which cost and performances should be evaluated, a simultaneous scheduling-and-allocation algorithm is presented, allowing resource sharing between nominal and checking data paths. The algorithm grants that the required checking periodicity is satisfied while minimizing additional costs in terms of functional units. Risk of error aliasing due to resource sharing is analyzed.