On the optimum checkpoint selection problem
SIAM Journal on Computing
Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems
IEEE Transactions on Computers
Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback
IEEE Transactions on Computers
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Synthesis of fault-tolerant and real-time microarchitectures
Journal of Systems and Software - Special issue on fault tolerance in real-time systems
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Rapid prototyping of fault-tolerant VLSI systems
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
High level synthesis for reconfigurable datapath structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Fault-secure algorithms for multiple-processor systems
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Heterogeneous built-in resiliency of application specific programmable processors
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
On-Line Fault Resilience Through Gracefully Degradable ASICs
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Self recovering controller and datapath codesign
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A low-redundancy approach to semi-concurrent error detection in data paths
Proceedings of the conference on Design, automation and test in Europe
Concurrent error recovery with near-zero latency in synthesized ASICs
Proceedings of the conference on Design, automation and test in Europe
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computer-Aided Design of Fault-Tolerant VLSI Systems
IEEE Design & Test
Efficient Self-Recovering ASIC Design
IEEE Design & Test
High-level synthesis of gracefully degradable ASICs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A high-level synthesis approach to design of fault-tolerant systems
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An error recoverable structure based on complementary logic and alternating-retry
Journal of Computer Science and Technology
On the Design of Self-Checking Controllers with Datapath Interactions
IEEE Transactions on Computers
RT level reliability enhancement by constructing dynamic TMRS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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In this paper, we will describe an integrated system for synthesizing self-recovering microarchitectures called ${\cal SYNCERE}$. In the ${\cal SYNCERE}$model for self-recovery, transient faults are detected using duplication and comparison, while recovery from transient faults is accomplished via checkpointing and rollback. ${\cal SYNCERE}$initially inserts checkpoints subject to designer specified recovery time constraints. Subsequently, ${\cal SYNCERE}$incorporates detection constraints by ensuring that two copies of the computation are executed on disjoint hardware. Towards ameliorating the dedicated hardware required for the original and duplicate computations, ${\cal SYNCERE}$imposes intercopy hardware disjointness at a sub-computation level instead of at the overall computation level. The overhead is further moderated by restructuring the pliable input representation of the computation. ${\cal SYNCERE}$has successfully derived numerous self-recovering microarchitectures. Towards validating the methodology for designing fault-tolerant VLSI ICs, we carried out a physical design of a self-recovering 16-point FIR filter.