On-Line Fault Resilience Through Gracefully Degradable ASICs

  • Authors:
  • Alex Orailoğlu

  • Affiliations:
  • Department of Computer Science and Engineering, University of California, San Diego, La Jolla CA 92093

  • Venue:
  • Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
  • Year:
  • 1998

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Abstract

We present two novel reconfigurationschemes, L/U reconfiguration and itsgeneralization, band reconfiguration, toachieve graceful degradation for generalmicroarchitecture datapaths. Upon detection of adatapath fault, hardware and algorithmicreconfigurations are performed dynamically through operationrescheduling and hardware rebinding. Instead ofa complete shuffling, the proposed scheme perturbs the originalschedule and binding in a systematic fashion. This regularity of thescheme allows well-structured design planning for the controller andthe datapath. The underlying microarchitecturesupporting such reconfiguration schemes isbriefly outlined. Experimental evidence indicates negligibleperformance and small hardware overheads.