High-level synthesis of gracefully degradable ASICs

Authors:
Wah Chan;A. Orailoglu
Affiliations:
Dept. of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA;Dept. of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

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Abstract

We propose a novel graceful degradation scheme, L/U reconfiguration, which can tolerate a single permanent fault in each hardware class of ASIC data paths. In the proposed scheme, dynamic hardware rebinding and operation rescheduling are performed by a systematic perturbation of the original configuration. A high-level synthesis procedure, which automatically generates such fault-tolerant systems, is also presented. Experiments show that our reconfigurable AISC designs, as compared to optimal nonfault-tolerant designs, achieve optimal pre-reconfiguration and near-optimal post-reconfiguration speed performance.