A VHDL primer
IEEE Transactions on Computers
Optimal Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the third session on Reliability in VLSI circuits : operation, manufacturing and design: operation, manufacturing and design
On-line test for fault-secure fault identification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis
IEEE Transactions on Computers
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Self-Checking Design in Eastern Europe
IEEE Design & Test
Efficient Modular Design of TSC Checkers for M-out-of-2M-Codes
IEEE Transactions on Computers
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Exploiting Idle Cycles for Algorithm Level Re-Computing
Proceedings of the conference on Design, automation and test in Europe
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance
Proceedings of the conference on Design, automation and test in Europe
Finite State Machine Synthesis with Concurrent Error Detection
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of parallel fault-secure encoders for systematic cyclic block transmission codes
Microelectronics Journal
Hi-index | 14.98 |
We consider the problem of designing self-checking controllers for controller/datapath architectures. We introduce the concept of intrinsically secure states. We present six alternative schemes based on parity checking, on 1-out-of-n checking, as well as on the observation that a self-checking sequential datapath can also be employed for control path self-checking by exploiting the concept of intrinsically secure control states. A high-level synthesis tool has been modified to automatically insert self-checking controllers and datapath units and is able to trade this self-checking property against other design objectives. We discuss the properties of each configuration and present experimental results and conclusions.