High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-level synthesis approach to optimum design of self-checking circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
High-level synthesis of recoverable VLSI microarchitectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis
IEEE Transactions on Computers
A low-redundancy approach to semi-concurrent error detection in data paths
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
Semi-Concurrent Error Detection in Data Paths
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Optimizing High-Level Synthesis for Self-Checking Arithmetic Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
A high-level synthesis approach to design of fault-tolerant systems
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On the Design of Self-Checking Controllers with Datapath Interactions
IEEE Transactions on Computers
IEEE Transactions on Computers
A middleware approach to achieving fault tolerance of Kahn process networks on networks on chips
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
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A high-level synthesis strategy is proposed for design of semiconcurrently self-checking devices. Attention is mainly focused on data path design. After identifying the reference architecture against which cost and performance are evaluated, a simultaneous scheduling-and-allocation strategy is presented for linear-code data flow graphs, allowing resource sharing between nominal and checking data paths. The proposed strategy is actually independent from a specific scheduling-and-allocation algorithm since it is essentially concerned with the introduction of the fault tolerance issue at high-abstraction level in any design environment. Conventional duplication with comparison, even if considered in a high-level synthesis strategy, leads to high circuit complexity increase. The proposed approach provides that the required checking periodicity is satisfied while minimizing additional functional units by means of maximum reuse of the resources available for the nominal computation as long as error detection ability is preserved. The strategy is then extended to deal with branches and loops in the data path. Risk of error aliasing due to resource sharing is analyzed.