High-level synthesis of recoverable VLSI microarchitectures

  • Authors:

  • Douglas M. Blough;Fadi J. Kurdahi;Seong Yong Ohm

  • Affiliations:

  • Georgia Institute of Technology, Atlanta;Univ. of California at Irvine, Irvine;Seoul Women's Univ., Seoul, Korea

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 1999

Quantified Score

Hi-index 0.00

Visualization

Abstract

Two algorithms that combine the operations of scheduling and recovery-point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit (FU) cost is minimized first and register cost second. The second algorithm minimizes a weighted sum of FU and register costs. Both algorithms are optimal according to their respective cost functions and require less than 10 min of central processing unit (CPU) time on widely used high-level synthesis benchmarks. The best previous result reported several hours of CPU time for some of the same benchmarks on a computer of similar computational power.