Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems
IEEE Transactions on Computers
High-level synthesis of fault-secure microarchitectures
DAC '93 Proceedings of the 30th international Design Automation Conference
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Phantom redundancy: a high-level synthesis approach for manufacturability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Allocation and Binding During Fault-Secure Microarchitecture Synthesis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
High Level Synthesis Techniques for Efficient Built-In-Self Repair
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Self recovering controller and datapath codesign
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A low-redundancy approach to semi-concurrent error detection in data paths
Proceedings of the conference on Design, automation and test in Europe
Concurrent error recovery with near-zero latency in synthesized ASICs
Proceedings of the conference on Design, automation and test in Europe
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
Efficient Self-Recovering ASIC Design
IEEE Design & Test
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