Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of Concurrent Error-Detectable VLSI-Based Array Dividers
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Error-Correcting Goldschmidt Dividers Using Time Shared TMR
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
High-level Synthesis of Data Paths with Concurrent Error Detection
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Transient and Intermittent Fault Recovery without Rollback
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Efficient time redundancy for error correcting inner-product units and convolvers
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Fault tolerant Newton-Raphson dividers using time shared TMR
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A 32-Bit Risc Processor with Concurrent Error Detection
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Lowering power consumption in concurrent checkers via input ordering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Synthesis of Low Power CED Circuits Based on Parity Codes
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Reducing Power Consumption in Memory ECC Checkers
ITC '04 Proceedings of the International Test Conference on International Test Conference
The development of high performance FFT IP cores through hybrid low power algorithmic methodology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Optimal algorithms for recovery point insertion in recoverable microarchitectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault secure datapath synthesis using hybrid time and hardware redundancy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 14.98 |
Errors introduced by radiation-induced single event upset and single event latchup in very deep submicron (VDSM) ICs necessitate concurrent error detection (CED) and correction. Power consumed by circuits used for detecting and correcting errors becomes an extra burden on the tight power budget of VDSM ICs. The triple-modular redundancy-based fault tolerance technique, which is traditionally used for error detection and correction, incurs over 200 percent power overhead. In this paper, we propose register-transfer level low-power on-demand error correction techniques. Proposed techniques implement an original computation and a recomputation in datapath and compare the results from two computations to monitor the health of circuit. A mismatch in results indicates faulty computation and a second recomputation is triggered to rectify the error. The proposed techniques can detect and correct SEU induced transient errors and detect SEL induced permanent errors with as little as 12 percent power overhead.