The development of high performance FFT IP cores through hybrid low power algorithmic methodology

Authors:
Wei Han;A. T. Erdogan;T. Arslan;M. Hasan
Affiliations:
University of Edinburgh, Edinburgh, Scotland, UK;University of Edinburgh, Edinburgh, Scotland, UK;University of Edinburgh, Edinburgh, Scotland, UK;University of Edinburgh, Edinburgh, Scotland, UK
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

This paper presents a solution based on parallel-pipelined architectures for high throughput and power efficient FFT IP cores. Low power consumption can be gained through the combination of hybrid low power algorithms and architectures. A number of IP cores have been implemented for the comparison of the impact of parameterization on power/area/speed performance. The results show that up to 55% and 52% power saving can be achieved by the combination of the above techniques for 64-point 4-parallel-pipelined FFT and 16-point 2-parallel-pipelined FFT respectively, as compared to R4SDC pipelined FFTs.