Reducing Power Consumption in Memory ECC Checkers

Authors:
Shalini Ghosh;Nur A. Touba;Sugato Basu
Affiliations:
Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX;Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX;Dept. of Computer Sciences, University of Texas, Austin, TX
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

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Abstract

In this paper, a method is proposed for reducing power consumption in memory ECC checker circuitry that provides SEC-DED. The degrees of freedom in selecting the parity check matrix are used to minimize power with little or no impact on area and delay. The power minimization method is applied to two popular SEC-DED codes: standard Hamming codes and odd-column-weight Hsiao codes. Experiments on actual memory traces of Spec and MediaBench benchmarks indicate that considering power in addition to area and delay when selecting the parity check matrix can result in power reductions of up to 27% for Hsiao codes and up to 41% for Hamming codes.