DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Embedded Memory Reliability: The SER Challenge
MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
Reducing Power Consumption in Memory ECC Checkers
ITC '04 Proceedings of the International Test Conference on International Test Conference
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
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As the VLSI technology scaling continues and the device dimension keeps shrinking, memories are more and more sensitive to soft errors. Memory cores usually occupy a large portion of an SOC and have significant impact on the chip reliability. Therefore error detection and correction (EDAC) techniques are commonly used for protecting the system against soft errors. This paper presents a novel EDAC scheme, which provides adaptive code rate for random access memories (RAMs). Under a certain reliability restriction, the proposed design allows more error bits than a conventional EDAC design.