An adaptive code rate EDAC scheme for random access memory
Proceedings of the Conference on Design, Automation and Test in Europe
Reliability analysis and improvement for multi-level non-volatile memories with soft information
Proceedings of the 48th Design Automation Conference
Product code schemes for error correction in MLC NAND flash memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nonlinear multi-error correction codes for reliable MLC NAND flash memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
International Journal of Computational Intelligence Studies
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ECC has been widely used to enhance flash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space for higher error correction capability to keep it usable even when there is a high noise level.