Flash Memories
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
Error Correction Codes for Non-Volatile Memories
Error Correction Codes for Non-Volatile Memories
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
FlashPower: a detailed power model for NAND flash memory
Proceedings of the Conference on Design, Automation and Test in Europe
VLSI implementation of BCH error correction for multilevel cell NAND flash memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nonvolatile Memory Partitioning Scheme for Technology-Based Performance-Reliability Tradeoff
IEEE Embedded Systems Letters
Wear unleveling: improving NAND flash lifetime by balancing page endurance
FAST'14 Proceedings of the 12th USENIX conference on File and Storage Technologies
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In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, we show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliability.