Reliability analysis and improvement for multi-level non-volatile memories with soft information

Authors:
Shih-Liang Chen;Bo-Ru Ke;Jian-Nan Chen;Chih-Tsun Huang
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan
Venue:
Proceedings of the 48th Design Automation Conference
Year:
2011

Citing 4
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Abstract

This paper presents the systematic methodology of error correction scheme using low-density parity check (LDPC) codes to improve the reliability and endurance of multi-level cell (MLC) non-volatile memories. Using our realistic error model, the LDPC architecture with the scheme of non-uniform reference voltages (NURV) is proposed to trade off among error correction capability, area, and throughput, which can improve the bit-error-rate significantly.