Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes

• Authors: Yuu Maeda;Haruhiko Kaneko
• Venue: DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
• Year: 2009

Conventional flash memories generally utilize simple error control codes, such as Hamming code and BCH code. In future high-density multilevel cell (MLC) flash memories, however, it is estimated that raw bit error rate (BER) will soar with increasing number of charge levels, and hence the conventional error control coding will not be sufficient for these memories. Low-density parity-check (LDPC) code is a class of strong error control codes which are adopted in practical wired/wireless communication systems, and hence the LDPC code is an important candidate for error control code in future MLC memories. Application of the LDPC code to MLC memory is not so straightforward as conventional error control codes because the LDPC code usually employs soft-input decoding to achieve low decoded BER, and hence analysis of the error probability is crucial, especially when nonbinary codes are applied. Therefore, this paper analyzes error characteristics of MLC flash memory from error control coding viewpoint, and then proposes an error control coding using nonbinary LDPC codes. Evaluation shows that the decoded BER of the nonbinary LDPC code is lower than that of conventional binary irregular LDPC code, and also demonstrates that nonbinary LDPC code defined by a parity-check matrix having average column weight w = 2.5 has lower decoded BER than nonbinary LDPC codes with w = 2 and 3.