Optimum LDPC decoder: a memory architecture problem
Proceedings of the 46th Annual Design Automation Conference
Low complexity LDPC decoding scheme for DMB-TH
CSNA '07 Proceedings of the IASTED International Conference on Communication Systems, Networks, and Applications
Block Based Video Data Hiding Using Repeat Accumulate Codes and Forbidden Zone Data Hiding
PCM '09 Proceedings of the 10th Pacific Rim Conference on Multimedia: Advances in Multimedia Information Processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reliability analysis and improvement for multi-level non-volatile memories with soft information
Proceedings of the 48th Design Automation Conference
A Reconfigurable TDMP Decoder for Raptor Codes
Journal of Signal Processing Systems
| Hi-index | 35.68 |
A turbo-decoding message-passing (TDMP) algorithm for sparse parity-check matrix (SPCM) codes such as low-density parity-check, repeat-accumulate, and turbo-like codes is presented. The main advantages of the proposed algorithm over the standard decoding algorithm are 1) its faster convergence speed by a factor of two in terms of decoding iterations, 2) improvement in coding gain by an order of magnitude at high signal-to-noise ratio (SNR), 3) reduced memory requirements, and 4) reduced decoder complexity. In addition, an efficient algorithm for message computation using simple "max" operations is also presented. Analysis using EXIT charts shows that the TDMP algorithm offers a better performance-complexity tradeoff when the number of decoding iterations is small, which is attractive for high-speed applications. A parallel version of the TDMP algorithm in conjunction with architecture-aware (AA) SPCM codes, which have embedded structure that enables efficient high-throughput decoder implementation, are presented. Design examples of AA-SPCM codes based on graphs with large girth demonstrate that AA-SPCM codes have very good error-correcting capability using the TDMP algorithm