Optimum LDPC decoder: a memory architecture problem

Authors:
Erick Amador;Renaud Pacalet;Vincent Rezard
Affiliations:
EURECOM, Sophia Antipolis, France;TELECOM ParisTech, Sophia Antipolis;Infineon Technologies France, Sophia Antipolis
Venue:
Proceedings of the 46th Annual Design Automation Conference
Year:
2009

Citing 3
Cited 0

Low complexity LDPC code decoders for next generation standards

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Non-fractional parallelism in LDPC decoder implementations

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A Turbo-Decoding Message-Passing Algorithm for Sparse Parity-Check Matrix Codes

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Abstract

This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.