VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AAECC'06 Proceedings of the 16th international conference on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
A Turbo-Decoding Message-Passing Algorithm for Sparse Parity-Check Matrix Codes
IEEE Transactions on Signal Processing
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DMB-TH (or DMB-T) is China Digital Multimedia Broadcasting standard for terrestrial and handheld. It features the RS-based Low-Density Parity-Check Codes with two information symbols as its channel coding scheme. In this paper, we propose a low complexity decoding scheme using the pipelined block-serial scheduling of computation and turbo decoding message passing algorithm. Rearranging the order of each component code and using single port SRAM allows pipeline schedule between consecutive layers, which reduces the latency by 2~3 times. We use the modified λ3 min-sum algorithm with only 6 bits uniform quantization which can achieve the same BER as that of floating point Jacobian BCJR with less than 0.15 dB SNR penalty even with rate 0.4 QAM64 in the AWGN channel.