Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Low Complexity Decoder Architecture for Low-Density Parity-Check Codes
Journal of Signal Processing Systems
Low complexity LDPC decoding scheme for DMB-TH
CSNA '07 Proceedings of the IASTED International Conference on Communication Systems, Networks, and Applications
Multiple-rate low-density parity-check codes with constant blocklength
IEEE Transactions on Communications
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Min-sum decoder architectures with reduced word length for LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Hi-index | 0.00 |
As feature sizes continue to decrease and clock rates and device count on a VLSI chip increase, it becomes increasingly more difficult to maintain yields at their present levels. Process variation, noise and spot defects create very costly problems for ...