Exploiting thread-level parallelism of irregular LDPC decoder with simultaneous multi-threading technique

Authors:
Xing Fang;Dong Wang;Shuming Chen
Affiliations:
School of Computer, National University of Defense Technology, Changsha, Hunan Province, P.R. China;School of Computer, National University of Defense Technology, Changsha, Hunan Province, P.R. China;School of Computer, National University of Defense Technology, Changsha, Hunan Province, P.R. China
Venue:
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Year:
2007

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Abstract

Irregular LDPC (Low Density Parity Check) code is a powerful error correction code in wireless communication applications. However, irregular LDPC decoder has limited instruction-level parallelism. This paper exploits the thread-level parallelism of irregular LDPC decoders with simultaneous multithreading (SMT) techniques. The simulations with random constructed parity check matrixes under different signal-to-noise ratios and three block lengths show that it can attain 16.7%-45.3% performance improvement by SMT technique with the area cost increasing by about 17.73%, which supposes that SMT is an efficient technique to improve the performance of irregular LDPC decoders.