Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
VLSI Concurrent Error Correcting Adders and Multipliers
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
Algorithm level re-computing: a register transfer level concurrent error detection technique
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IEEE Transactions on Computers
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Fault tolerance can be achieved by using time redundancy with modest hardware overhead at the expense of computation time. In this paper the REcomputing with Triplication With Voting (RETWV) technique is applied to complex arithmetic units, such as inner product units and convolvers for concurrent error correction. Hardware complexity, delay, and throughput of the RETWV concurrent error correcting inner product units are analyzed and compared. It is seen that RETWV designs can be faster than the conventional design. That is, in addition to their concurrent error correcting capability, the throughput of RETWV designs is higher than that of their nonredundant counterparts. This result is significant because this shows that the RETWV technique, which is a time redundancy approach, can be used in high performance systems.