High-level Synthesis of Data Paths with Concurrent Error Detection

Authors:
Anna Antola;Vincenzo Piuri;Mariagiovanna Sami
Affiliations:
-;-;-
Venue:
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
1998

Citing 0
Cited 4

Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors

IEEE Transactions on Computers
Reliability-Centric High-Level Synthesis

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An ILP Formulation for Reliability-Oriented High-Level Synthesis

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique

IEEE Transactions on Computers

Quantified Score

Hi-index	0.01

Visualization

Abstract

High-level synthesis of data paths with concurrent self-checking abilities is discussed to balance redundancy, latency, and checking effectiveness. The nominal and the checking computations are scheduled and allocated contemporaneously by using a force-directed approach to limit the number of redundant units required to achieve detection within the latency of the nominal computation only. Resource sharing between the nominal and the checking computation is used to minimise the redundancy, while keeping error aliasing as reduced as possible.