IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
High level synthesis for reconfigurable datapath structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-level Synthesis of Data Paths with Concurrent Error Detection
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
The Effect of Threshold Voltages on the Soft Error Rate
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Reliability-aware Co-synthesis for Embedded Systems
Journal of VLSI Signal Processing Systems
A variation-tolerant scheduler for better than worst-case behavioral synthesis
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Timing variation-aware scheduling and resource binding in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Reliability decisions taken early in system design can bring significant benefits in terms of design quality. This paper presents a 0-1 integer linear programming (ILP) formulation for reliability-oriented high-level synthesis that addresses the soft error problem. The proposed approach tries to maximize reliability of the design while observing the bounds on area and performance, and makes use of our reliability characterization of hardware components such as adders and multipliers. We implemented the proposed approach, performed experiments with several example designs, and compared the results with those obtained by a prior proposal. Our results show that incorporating reliability as a first-class metric during high-level synthesis brings significant improvements on the overall design reliability.