A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Logic synthesis
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Incorporating testability considerations in high-level synthesis
Journal of Electronic Testing: Theory and Applications
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Introduction to High-Level Synthesis
IEEE Design & Test
Introduction to the Scheduling Problem
IEEE Design & Test
Behavioral Synthesis for Easy Testability in Data Path Allocation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A test synthesis technique using redundant register transfers
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Channel-based behavioral test synthesis for improved module reachability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A low-redundancy approach to semi-concurrent error detection in data paths
Proceedings of the conference on Design, automation and test in Europe
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
Inserting Scan at the Behavioral Level
IEEE Design & Test
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An RTL Methodology to Enable Low Overhead Combinational Testing
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Building Block BIST Methodology for SOC Designs: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Addressing Early Design-For-Test Synthesis in a Production Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Co-evolutionary high-level test synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Co-Testing: Granting Testability in a Codesign Environment
Integrated Computer-Aided Engineering
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
Design for testability reuse in synthesis for testability
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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