Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Unified data path allocation and BIST intrusion
Integration, the VLSI Journal
A new approach to built-in self-testable datapath synthesis based on integer linear programming
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Scheduling and module assignment for reducing BIST resources
Proceedings of the conference on Design, automation and test in Europe
Cost/Quality Trade-off in Synthesis for BIST
Journal of Electronic Testing: Theory and Applications
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Introduction to Evolutionary Computing
Introduction to Evolutionary Computing
Datapath synthesis using a problem-space genetic algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a solution to the problem of making a trusted third-party authentication protocol fault tolerant. We applied the general solution to the Needham and Schroeder and Kerberos authentication protocols. Finally, we discuss the implementation ...