Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Design for testability reuse in synthesis for testability
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
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This paper details our allocation for Built-in Self Test (BIST) technique used by the core part of our Testability Allocation and Control System (TACOS) called IDAT. IDAT tool objective is to fulfill the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the final testable circuit. The allocation process of BIST resources in the data-path is driven by two trade-off techniques performed in order to: (1) at the local level, select the optimal set of Functional Units (FUs) to be BISTed, using a new testability analysis method and (2) at the global level, for each selected FU of this set, choose either to allocate its BIST version (when available in a library) or to connect it to an internal Test Pattern Generator (TPG) and Test Results Checker (TRC). When necessary, a last step of the process is the allocation of scan chains used to test the remaining untested interconnections. Experiments show the results of our allocation for BIST technique on three benchmarks.