Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
VLSI design synthesis with testability
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An architecture for synthesis of testable finite state machines
EURO-DAC '90 Proceedings of the conference on European design automation
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Lower bounds on test resources for scheduled data flow graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Introducing redundant computations in a behavior for reducing BIST resources
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Estimation of BIST Resources During High-Level Synthesis
Journal of Electronic Testing: Theory and Applications
On ILP formulations for built-in self-testable data path synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Scheduling and module assignment for reducing BIST resources
Proceedings of the conference on Design, automation and test in Europe
Introducing redundant computations in RTL data paths for reducing BIST resources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost/Quality Trade-off in Synthesis for BIST
Journal of Electronic Testing: Theory and Applications
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Addressing Early Design-For-Test Synthesis in a Production Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testability Insertion in Behavioral Descriptions
ISSS '96 Proceedings of the 9th international symposium on System synthesis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
Journal of Electronic Testing: Theory and Applications
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
Transforming behavioral specifications to facilitate synthesis of testable designs
ITC'94 Proceedings of the 1994 international conference on Test
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