On ILP formulations for built-in self-testable data path synthesis

A scheduling and resource allocation algorithm for hierarchical signal flow graphs

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference

A data path synthesis method for self-testable designs

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference

Data path allocation for synthesizing RTL design with low BIST area overhead

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

An improved method for RTL synthesis with testability tradeoffs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Synthesis and Optimization of Digital Circuits

Synthesis and Optimization of Digital Circuits

Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner

Test session oriented built-in self-testable data path synthesis

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Automated data-memory synthesis: a formal method for the specification, analysis, and design of register-transfer level digital logic

Automated data-memory synthesis: a formal method for the specification, analysis, and design of register-transfer level digital logic

Microarchitectural synthesis for rapid BIST testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems