A scheduling and resource allocation algorithm for hierarchical signal flow graphs
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Lower bounds on test resources for scheduled data flow graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Introducing redundant computations in a behavior for reducing BIST resources
DAC '98 Proceedings of the 35th annual Design Automation Conference
On ILP formulations for built-in self-testable data path synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Microarchitectural synthesis for rapid BIST testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A high-level built-in self-test (BIST) synthesisinvolves several tasks such as system register assignment,interconnection assignment, and BIST register assignment.Existing high-level BIST synthesis methods perform thetasks sequentially at the cost of global optimality. Weproposed a new approach based on an integer linearprogramming (ILP) [18]. Our method achieves optimalsolutions for most circuits in hardware overhead, but ittakes a long processing time. In this paper, we present aheuristic method to address this problem. The heuristicpartitions a given data flow graph into smaller regionsbased on control steps and applies the ILP for each regionsuccessively. Our heuristic reduces the processing time byseveral orders of magnitude, while the quality of thesolution is slightly compromised. We present experimentalresults for six circuits and compare the results with otherBIST synthesis methods.