Crafting a compiler
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Optimal replication for min-cut partitioning
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for testability
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Handbook of Digital Signal Processing: Engineering Applications
Handbook of Digital Signal Processing: Engineering Applications
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Pipelines with internal buffers
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Bounds on evacuation time for deflection routing
Distributed Computing
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Recently, several high level synthesis approaches have been proposed to synthesize testable data paths from behavioral specifications. This paper introduces a novel technique to transform behavioral specifications, such that an existing behavioral test synthesis system can generate area-efficient, testable designs with significantly lower partial scan overhead. Experimental results demonstrate the significant savings in partial scan overhead when the transformation is applied before using the behavioral test synthesis system to synthesize 100% test-efficient designs.