ACM Computing Surveys (CSUR)
Improving the throughput of a pipeline by insertion of delays
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Improving the throughput of pipelines with delays and buffers.
Improving the throughput of pipelines with delays and buffers.
Optimizing resource utilization and testability using hot potato techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
High-level specification and efficient implementation of pipelined circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Transforming behavioral specifications to facilitate synthesis of testable designs
ITC'94 Proceedings of the 1994 international conference on Test
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Concurrent or overlapped processing of more than one task is a common technique used in many computer architectures to increase the throughput. A pipeline is one such form consisting of a set of hardware segments which can be operated in an overlapped fashion. The existing and many proposed pipelines assume that a task must flow synchronously, without wait or preemption, from segment to segment for its execution. In this paper we propose a pipeline model in which priority buffers are provided at every segment to control the flow of tasks. Several different priority implementations are analyzed assuming periodic arrivals of tasks. The characteristics studied are, queue size, wait time and throughput. It is shown that the theoretical maximum throughput of a pipeline is attainable with the use of internal buffers. Moreover, it is shown that a substantial degree of freedom in scheduling of tasks is achieved by these methods.