Communicating sequential processes
Communicating sequential processes
Statecharts: A visual formalism for complex systems
Science of Computer Programming
Programming in Occam 2
Parallel program design: a foundation
Parallel program design: a foundation
Synthesis from production-based specifications
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Term rewriting and all that
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
Pipelines with internal buffers
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
High-level automatic pipelining for sequential circuits
Proceedings of the 14th international symposium on Systems synthesis
High-level optimization of pipeline design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Synthesizing synchronous elastic flow networks
Proceedings of the conference on Design, automation and test in Europe
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This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.