Compilation for a high-performance systolic array
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
URPR—An extension of URCR for software pipelining
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems
IEEE Transactions on Computers
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Optimization of horizontal microcode generation for loop structures
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Optimizing horizontal microprograms for vectorial loops with timed petri nets
ICS '88 Proceedings of the 2nd international conference on Supercomputing
An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Sehwa: A program for synthesis of pipelines
25 years of DAC Papers on Twenty-five years of electronic design automation
Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
The floating point performance of a superscalar SPARC processor
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Datapath scheduling for two-level pipelining
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Register requirements of pipelined processors
ICS '92 Proceedings of the 6th international conference on Supercomputing
Enhanced modulo scheduling for loops with conditional branches
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Minimum register requirements for a modulo schedule
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Unrolling-based optimizations for modulo scheduling
Proceedings of the 28th annual international symposium on Microarchitecture
IEEE Transactions on Parallel and Distributed Systems
A reduced multipipeline machine description that preserves scheduling constraints
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Loop optimization for horizontal microcoded machines
ICS '90 Proceedings of the 4th international conference on Supercomputing
An evaluation of functional unit lengths for single-chip processors
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Modulo scheduling for the TMS320C6x VLIW DSP architecture
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Overview of a high-performance programmable pipeline structure
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Vector register design for polycyclic vector scheduling
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory
International Journal of Parallel Programming
Maximum Performance Pipelines With Switchable Reservation Tables
IEEE Transactions on Computers
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
An adaptive multimicroprocessor array computing structure for radar signal processing applications
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Pipelines with internal buffers
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Co-Scheduling Hardware and Software Pipelines
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
An Enhanced Co-Scheduling Method using Reduced MS-State Diagrams
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Software pipelining: an effective scheduling technique for VLIW machines
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Modulo scheduling without overlapped lifetimes
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
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A pipeline is defined to be a collection of resources, called segments which can be kept busy simultaneously. A task once initiated, flows from segment to segment for its execution. A collision occurs if two or more tasks attempt to use the same segment at the same time. The collision characteristics of a pipeline with respect to a schedule of task initiations are investigated. A methodology is presented for modifying the collision characteristics with the insertion of delays so as to increase the utilization of segments and hence the throughput under appropriate scheduling.