Overview of a high-performance programmable pipeline structure

Authors:
Franc¸ois Bodin;Franc¸ois Charot;Charles Wagner
Affiliations:
IRISA, Campus de Beaulieu, 35042 Rennes-Cedex, France;IRISA, Campus de Beaulieu, 35042 Rennes-Cedex, France;IRISA, Campus de Beaulieu, 35042 Rennes-Cedex, France
Venue:
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Year:
1989

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Abstract

This paper aims at describing a high-performance programmable pipeline architecture consisting of a linear array of PCS processors. The PCS processor which is capable of performing 20 million floating-point operations per second (20 MFLOPS) has been built from off-the-shelf chips on a wire-wrapped board. The prototype processor is attached to a SUN-3 workstation.Efficient microcode is generated using the microcode compiler that has been designed and implemented. The microcode optimization includes microcode compaction and loop optimization using the software pipelining technique. Another loop optimization technique based on the unrolling is also outlined. Preliminary results obtained on vector benchmarks are given.