Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Advances in Petri Nets 1988
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
Improving the throughput of a pipeline by insertion of delays
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
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This paper deals with the minimization of the asymptotic latency of horizontal microprograms performing vectorial loops. On a quite general architecture model, we show that all the constraints can be formalized to give a cyclic scheduling problem, modelled with a Timed Petri net. To analyse the net behaviour, a bivalued resolution graph is build. A critical cycle of this graph leads to optimal microprograms whose structure is independent on the number of iterations. This approach is then extended to uniform recurrences.