Minimum register requirements for a modulo schedule

Authors:
Alexandre E. Eichenberger;Edward S. Davidson;Santosh G. Abraham
Affiliations:
Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, MI;Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, MI;Hewlett Packard Laboratories, 1501 Page Mill Road, Palo Alto, CA
Venue:
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Year:
1994

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Abstract

Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a modulo reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. This method demonstrates the potential of lifetime-sensitive modulo scheduling and is useful in evaluating the performance of lifetime-sensitive modulo scheduling heuristics.