Register pressure in software-pipelined loop nests: fast computation and impact on architecture design

  • Authors:

  • Alban Douillet;Guang R. Gao

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Delaware, Newark, DE;Department of Electrical and Computer Engineering, University of Delaware, Newark, DE

  • Venue:
  • LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
  • Year:
  • 2005

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Abstract

Recently the Single-dimension Software Pipelining (SSP) technique was proposed to software pipeline loop nests at an arbitrary loop level [18,19,20]. However, SSP schedules require a high number of rotating registers, and may become infeasible if register needs exceed the number of available registers. It is therefore desirable to design a method to compute the register pressure quickly (without actually performing the register allocation) as an early measure of the feasibility of an SSP schedule. Such a method can also be instrumental to provide a valuable feedback to processor architects in their register files design decision, as far as the needs of loop nests are concerned. This paper presents a method that computes quickly the minimum number of rotating registers required by an SSP schedule. The results have demonstrated that the method is always accurate and is 3 to 4 orders of magnitude faster on average than the register allocator. Also, experiments suggest that 64 floating-point rotating registers are in general enough to accommodate the needs of the loop nests used in scientific computations.