Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching

  • Authors:

  • Zhong Wang;Timothy W. O'neil;Edwin H.-M. Sha

  • Affiliations:

  • Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN 46556, USA;Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN 46556, USA;Department of Computer Science, University of Texas at Dallas, Richardson, TX 75083

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2001

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Abstract

Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As a result, a variety of techniques has been devised to hide that performance gap, from intermediate fast memories (caches) to various prefetching and memory management techniques for manipulating the data present in these caches. In this paper we propose a new memory management technique that takes advantage of access pattern information that is available at compile time by prefetching certain data elements before explicitly being requested by the CPU, as well as maintaining certain data in the local memory over a number of iterations. In order to better take advantage of the locality of reference present in loop structures, our technique also uses a new approach to memory by partitioning it and reducing execution to each partition, so that information is reused at much smaller time intervals than if execution followed the usual pattern. These combined approaches—using a new set of memory instructions as well as partitioning the memory—lead to improvements in total execution time of approximately 25% over existing methods.