Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
BDDMAP: a technology mapper based on a new covering algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Technology adaption in logic synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A Design For Test Perspective on I/O Management
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
On Synthesizing Circuits With Implicit Testability Constraints
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Avoiding Unknown States When Scanning Mutually Exclusive Latches
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Technology Independent Boundary Scan Synthesis (Technology and Physical Issues)
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The maturity of high-level synthesis systems has enabledthe u,se of design-for-test (DFT) methods early inthe design phase. Early DFT synthesis ensures that theprocessing and transformation of multibit register variables,clock-gating, and initialization specifications areconsistent with the high-level specification. Functionaland test logic can be optimized in the same pass withoutthe need for an iterative timing closure procedure.It. allows designers to keep a single design source whilesynthesizing and mapping the logic to multiple technologylibraries. This paper addresses the implementation ofan early DFT synthesis system and presents experimentalresults to compare the early mode insertion approachwith a late-mode approach.