An ALGOL-like computer design language
Communications of the ACM
DAC '80 Proceedings of the 17th Design Automation Conference
Quality of designs from an automatic logic generator (ALERT)
DAC '70 Proceedings of the 7th Design Automation Workshop
LSS: a system for production logic synthesis
IBM Journal of Research and Development
A case study in silicon compilation software engineering, HVDEV high voltage device layout generator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An overview of logic synthesis systems
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
TRIP: an automated technology mapping system
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAGON: Technology binding and local optimization by DAG matching
25 years of DAC Papers on Twenty-five years of electronic design automation
Timing optimization for multi-level combinational networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
BDDMAP: a technology mapper based on a new covering algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
MILO: a microarchitecture and logic optimizer
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Synthesis and Verification
System-on-Chip Testability Using LSSD Scan Structures
IEEE Design & Test
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Addressing Early Design-For-Test Synthesis in a Production Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
UbiComp'06 Proceedings of the 8th international conference on Ubiquitous Computing
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Systems which synthesize logic implementations from specifications have moved, under the pressure of production requirements, from Boolean minimizers to procedures attempting to satisfy a wider range of criteria. Gate or cell count, taken as a measure of area, continues to be a major factor in design acceptability, but timing constraints, testability, wirability, and efficient use of available primitives are important as well. Additional information, such as “don't care” conditions, can be used to improve the design quality. This paper describes how these requirements are specified to and enforced by the Logic Synthesis System (LSS), a tool which has been used in production on gate array chips. Trade-offs between varying requirements, and their effect on the logic produced, are discussed and illustrated with a standard set of examples.