DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Multilevel synthesis minimizing the routing factor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
Performance-oriented technology mapping
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Minimizing the routing cost during logic extraction
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Limits of using signatures for permutation independent Boolean comparison
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Technology mapping for low power in logic synthesis
Integration, the VLSI Journal
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Technology adaption in logic synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Optimal Code Generation for Expression Trees
Journal of the ACM (JACM)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Technology Mapping for VLSI Circuits Exploiting Boolean Properties and Operations
Technology Mapping for VLSI Circuits Exploiting Boolean Properties and Operations
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Logic and system design for low power consumption
Logic and system design for low power consumption
Logic decomposition during technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Technology mapping transforms a technology independent logic network into gates implemented in a technology library. This chapter focuses on the three phases of technology mapping: decomposition, pattern matching and covering. Traditionally, a lot of work has been focused on tree mapping algorithms, but since most practical circuits are DAGs, DAG mapping algorithms are gaining importance. Different objective functions, namely delay, area, power and reliability motivate the use of different algorithms. Future challenges are outlined.