Routability-driven fanout optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
An Approach to Multilevel Boolean Minimization
Journal of the ACM (JACM)
M32: a constructive multilevel logic synthesis system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Estimation and removal or routing congestion (discussion session)
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Technology mapping for minimizing gate and routing area
Proceedings of the conference on Design, automation and test in Europe
Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Logic Synthesis and Verification
Bounding the efforts on congestion optimization for physical synthesis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
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