DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Minimizing the routing cost during logic extraction
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Timing closure based on physical hierarchy
Proceedings of the 2002 international symposium on Physical design
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Congestion-Aware Logic Synthesis
Proceedings of the conference on Design, automation and test in Europe
Layout Driven Decomposition with Congestion Consideration
Proceedings of the conference on Design, automation and test in Europe
An integrated logical and physical design flow for deep submicron circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analysis of the wire-load model uncertainty problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this era of Deep Sub-Micron (DSM) technologies, interconnects are becoming increasingly important as their effects strongly impact the integrated circuit (IC) functionality and performance. Moreover, logic block size is no longer determined exclusively by total cell area, and is often limited by wiring resources, yet synthesis optimization objectives are focused on minimizing the number and size of library cells. Methodologies that incorporate congestion within the logic synthesis have been proposed in the past. However, in [15] and [16] it was demonstrated that predicting the true congestion prior to layout is not possible, since different layout regions can have very different routing demands, and the effectiveness of any congestion minimization approach can only be evaluated after routing is completed within the assigned die size. In these works, congestion minimization efforts at the synthesis level are controlled by means of a global weighting factor in the technology mapping cost function. Nevertheless, due to the lack of accurate congestion models, during logic synthesis it is not possible to estimate a priori which values of the congestion minimization factor will yield a congestion-free synthesized netlist. In this paper, we derive practical bounds, which limit the search space for an optimal congestion minimization factor that produces a routable netlist within fixed floorplan constraints. Although we believe that a top-down single-pass congestion-aware logic synthesis is not going to work in general, the bounds obtained in this work can be used in a practical and robust congestion minimization methodology, which can be implemented into any commercial design flow.