Corolla based circuit partitioning and resynthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Concurrent logic restructuring and placement for timing closure
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Edge separability based circuit clustering with application to circuit partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Bounding the efforts on congestion optimization for physical synthesis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Metrics for structural logic synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
A predictive distributed congestion metric and its application to technology mapping
Proceedings of the 2004 international symposium on Physical design
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
Proceedings of the 2005 international symposium on Physical design
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
A new incremental placement algorithm and its application to congestion-aware divisor extraction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logical and physical restructuring of fan-in trees
Proceedings of the 19th international symposium on Physical design
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times.With the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. While this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure.In our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. In addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.