Concurrent logic restructuring and placement for timing closure

Authors:
Jinan Lou;Wei Chen;Massoud Pedram
Affiliations:
Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA;Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA;Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
Venue:
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Year:
1999

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Abstract

In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and then generates the set of non-inferior re-mapping solutions for each supercell. The best mapping and placement solutions for all super-cells are obtained by solving a generalized geometric programming (GGP) problem. The process of identifying and optimizing the critical paths is iterated until timing closure is achieved. Experimental results on a set of MCNC benchmarks demonstrate the effectiveness of our algorithm.