A polynomial algorithm for the min-cut linear arrangement of trees
Journal of the ACM (JACM)
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Logic extraction based on normalized netlengths
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Logic synthesis for vlsi design
Logic synthesis for vlsi design
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
A simultaneous routing tree construction and fanout optimization algorithm
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Gate sizing with controlled displacement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
An &agr;-approxmimate algorithm for delay-constraint technology mapping
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Concurrent logic restructuring and placement for timing closure
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An integrated algorithm for combined placement and libraryless technology mapping
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Technology-based transformations
Logic Synthesis and Verification
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Addressing the timing closure problem by integrating logic optimization and placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Placement-driven technology mapping for LUT-based FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of minimizing the post-layout area. The proposed algorithm relies on generation of gate-area versus cut-width curves using a dynamic programming approach. A novel design flow, which extends this algorithm to minimize the circuit delay and handle general DAG structures, is also presented. Experimental results on MCNC benchmarks are reported.