Integrated power supply planning and floorplanning

Authors:
I-Min Liu;Hung-Ming Chen;Tan-Li Chou;Adnan Aziz;D. F. Wong
Affiliations:
Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas;Computer Sciences, The University of Texas at Austin, Austin, Texas;Strategic CAD Labs., Design Technology, Intel Corporation, Hillsboro, Oregon;Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas;Computer Sciences, The University of Texas at Austin, Austin, Texas
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

Citing 18
Cited 5

Optimum design of reliable IC power networks having general graph topologies

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Network flows: theory, algorithms, and applications

Network flows: theory, algorithms, and applications
Rectangle-packing-based module placement

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Computational geometry: algorithms and applications

Computational geometry: algorithms and applications
Power supply noise analysis methodology for deep-submicron VLSI chip design

DAC '97 Proceedings of the 34th annual Design Automation Conference
An exact solution to simultaneous technology mapping and linear placement problem

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with pre-placed modules

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with range constraint

ISPD '99 Proceedings of the 1999 international symposium on Physical design
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An O-tree representation of non-slicing floorplan and its applications

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design

DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Planning buffer locations by network flows

ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning

ISPD '00 Proceedings of the 2000 international symposium on Physical design
Integrated floorplanning and interconnect planning

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect-driven floorplanning

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness

Computers and Intractability: A Guide to the Theory of NP-Completeness
Automatic floorplan design

DAC '82 Proceedings of the 19th Design Automation Conference

Efficient power/ground network analysis for power integrity-driven design methodology

Proceedings of the 41st annual Design Automation Conference
Floorplanning with power supply noise avoidance

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Heuristic power/ground network and floorplan co-design method

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Parallel Simulated Annealing Approach for Floorplanning in VLSI

ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply voltage can result in slower cell switching, or even circuit failure. Nevertheless, most floorplanning methodologies have ignored power supply considerations. Thus, the resulting floorplan may suffer from local hot spots and insufficient power supply for certain circuit blocks. In this paper, we present an optimal power supply planning algorithm based on network flow to shorten the current paths from power bumps to local power supply wirings. We have incorporated our algorithm into a floorplanning algorithm for integrated floorplanning and power supply planning. Experimental results are encouraging.